July 2, 2025

Round-up

Highlights

1. Senate ups the ante on fab incentives. A bill that sailed through the upper chamber last night lifts the investment tax credit for new U.S. semiconductor plants from 25 % to 35 %, sweetening economics for every green-field project now on the drawing board¹.
2. Intel signals a pivot from 18A to 14A. CEO Lip-Bu Tan is weighing whether to stop marketing the costly 18A node externally and push customers straight to the upcoming 14A process—an about-face that could trigger a multi-billion-dollar write-off but promises higher performance per watt than TSMC’s N2²³.
3. U.S.–Japan leap ahead in public EUV R&D hubs. Government-backed institutes in Albany and Tsukuba have installed EUV scanners, while South Korea’s “mini-fab” slipped to older ArF tools, potentially redrawing early-node learning curves⁴.

Other developments

• FTC issues a second-round data request on SoftBank’s $6.5 billion bid for Arm-based server vendor Ampere, signalling a lengthier antitrust review⁵.
• TSMC Arizona shuffles its board: long-time U.S. chief Rick Cassidy steps down; fab president Rose Castanares takes the seat ahead of mass-production ramps⁶.
• UMC is rumored to join forces with Intel on a 6 nm line, ending an eight-year retreat from advanced nodes⁷.
• Consumer DDR4 spot prices keep rising but PC-grade parts sag, hinting at another mixed quarter for memory makers⁸.

Did you know? A single high-NA EUV scanner now costs ≈ $180 million, or roughly the price of building an entire 200 mm fab in the early 2000s⁴.

In-depth

1 | Government & Corporate Policy

• 35 % U.S. fab credit

  • House leaders aim to pass the measure before the July 4 recess; firms breaking ground before 2026 remain eligible¹.
  • Analysts say the richer credit cuts net capital intensity for leading-edge plants by 8-10 %.

• SoftBank–Ampere antitrust drag

  • The FTC’s “second request” freezes the deal timetable and may force concessions on cloud-server pricing or Arm core licensing⁵.
  • SoftBank insists the buy will bolster U.S. AI infrastructure spending.

• Public EUV testbeds

  • The U.S. NSTC’s Albany complex begins shared-tool access this month; a high-NA scanner arrives in 2026⁴.
  • Japan’s AIST facility targets 2027, while Korea’s EUV plan is on hold, raising fears of talent flight.

• Export-control enforcement

  • A Singapore court postponed the DeepSeek GPU-smuggling case to August; prosecutors cite “cross-border evidence” after Nvidia chips were rerouted through fake end users⁹.

2 | Economics, Finance & Business Outlook

• Intel roadmap shake-up

  • Internal proposals would limit 18A to Intel products and a handful of cloud contracts, with external foundry clients steered to 14A risk production in 2027²³.
  • Potential write-offs could land in Q4, but Tan believes a cleaner offering will lure Apple and Nvidia.

• UMC’s comeback bid

  • Nikkei reports a joint Arizona module with Intel that could extend their 12 nm deal down to 6 nm; cap-ex still lags rivals by > $5 billion⁷.
  • Asset-light model may rely on Intel for EUV capacity sharing.

• TSMC Arizona board shuffle

  • Leadership transition is timed to the fab’s second-phase tool move-in next quarter; observers expect smoother U.S. state-aid negotiations⁶.

• Memory pricing split

  • Spot 16 Gb DDR4 parts rose again this week, but 8 Gb PC DRAM slipped 1.5 %, a divergence TrendForce links to sluggish consumer PC builds⁸.

3 | Technology & R&D

• 14A technical edge

  • Intel’s 14A promises 15-20 % speed and 25-35 % power gains over 18A, using second-gen backside power delivery and enabling chip-on-wafer-on-substrate variants³.

• AI server growth dialed back

  • Export restrictions on top-bin GPUs trim TrendForce’s 2025 AI-server shipment forecast to +24.3 % YoY; CSPs pivot to in-house ASICs and TPU v6e chips¹⁰.

• CAMM2 smashes DDR5-10000

  • G.Skill hit 10 GT/s on a 64 GB CAMM2 module atop a modified Asus Z890 board—pointing to thinner, faster memory for future laptops and edge servers¹¹.

• Underfill simulation breakthrough

  • Moldex3D’s hybrid 3D/2D model slashes compute time for CoWoS-class multi-chip modules while matching glass-substrate flow experiments—potentially accelerating advanced-package design cycles¹².

Footnotes